In general, a semiconductor system performs a fail test in order to improve reliability to detect faulty semiconductor memory devices. The fail test is performed by the following process: identical data are written into memory cells and then read to check whether the semiconductor memory device fails the fail test. Whether the semiconductor memory device fails (has a fail) may be determined based on whether the written data are identical to the read data. That is, when the written data are identical to the read data the semiconductor memory device is determined to be a good device, and when the written data are different from the read data the semiconductor memory device is determined to be a bad, or fail, device.
After the fail test, information on the fail of the semiconductor device is internally stored. The store operation is performed in synchronization with a delayed clock signal which is internally generated during a read operation, and the delayed clock signal is generated by delaying a clock signal generated in synchronization with a read command.
However, when a skew occurs in the semiconductor memory device due to a PVT (Process, Voltage, and Temperature) variation, it is difficult to adjust timing at which information on a memory cell determined as a fail cell is stored in synchronization with the delayed clock signal. Therefore, it may be difficult to store the fail information of the semiconductor memory device in a reliable way.